Responsibilities

• Own and be responsible for pre-tape out quality for digital SOC modules on the MCU
• Explore architecture and develop micro-architecture.
• RTL development for IPs and SOCs using Verilog
• 3rd party IP identification, selection, and integration
• Collaboration with verification and FPGA teams in test plan development and debug
• Collaborate with the Physical Design team to close the design on timing and power targets
• Assist in silicon bring-up and validation;
• Run tool for quality checks (LINT, CDC, and RDC) and fix/waive the issues

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