Responsibilities

• Develop and review random-sequence testbench content by analyzing block-level specification documents for new and legacy features.
• Build, enhance, and support SVA/SystemVerilog assertion-based verification environments, including UVM testbenches, for subsystem and full-chip Verilog verification.
• Execute verification workflows including modeling and simulation using industry-standard simulators, and drive RTL code coverage and functional coverage closure.
• Implement, enhance, and support automation tools and workflows to improve design verification efficiency using scripting languages such as Perl and Python.
• Develop synthesizable NAND models to enable FPGA emulation of ASIC controller designs and contribute to cross-group communication and standardization.

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