Position Responsibilities

• Responsible for STA analysis and convergence throughout the ASIC cycle
• Responsible for finding solution for intricate timing paths (Digital, analog and mixed signal)
• Facilitate STA methodology in collaboration with other STA leaders
• Generate timing constraints for multiple ASICs and FPGAs
• Generate tool independent timing constraints that will work for synthesis, place & route and static timing analysis
• Responsible for intricate cross domain timing path closure
• Extract timing information from circuit analysis and develop primary input setup/hold timing constraints as well as primary output required arrival time (RAT) and skew timing constraints
• Programming skills with Python, TCL, Perl, Unix shell etc.
• Help train new engineers 
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